Compact Modeled SOI MOSFET Circuits

SOI means Silicon on Insulator. This type of transistors has Silicon-Insulator-Silicon substrate which is different from conventional MOSFET structure where metal layer is used on the top of Insulator [1, . Now a days, the width of the oxide of a MOSFET is reduced from 300nm to 1.2nm and even less with scaling in technology. If it is further reduced, the leakage problems (majorly Sub-threshold Leakage) come into play . In order to solve this problem and let the technology to scale further, we use a small Silicon strip on the oxide leading to next generation SOI MOSFET’s. It provides an added advantage of reduction of parasitic capacitance which improves the performance and thereby increases the speed of operation by decreasing the delay values. In this paper, we use the BSIMSOI Model to simulate the analog circuits using EDA tools like Cadence and thereby verify the modeling of SOI MOSFET’s. Index Terms BSIM, Sub Threshold Leakage SOIMOSFET, SOS (silicon on sapphire).